The Wafer Level Chip Size Packaging (WLCSP) technology is a technology in which a packaging test is performed on a wafer and then the wafer is cut to obtain a single chip finished product, and a size of the packaged chip is totally the same as that of a die. The wafer level chip size packaging technology totally subverts the conventional package, such as Ceramic Leadless Chip Carrier and Organic Leadless Chip Carrier and the like, and meets market requirements of being lighter, smaller, shorter, thinner and cheaper for microelectronic products. A size of the chip packaged with the wafer level chip size packaging technology can be highly miniaturized, and a chip cost is decreased significantly with decrease of the chip size and increase of the wafer size. The wafer level chip size packaging technology is a technology that may integrate the IC design, the wafer fabrication, the package test and the substrate fabrication, which is a hot topic and represents a future development trend in the current package field.
The fan out wafer level packaging technology is one of the wafer level packaging technologies. The fan out wafer level packaging method includes: forming a peeling film on a surface of a carrier wafer; forming a dielectric layer on a surface of the peeling film; forming a re-wiring metal layer and a metal electrode in the dielectric layer; flipping the chip to electrically connect to the metal electrode; forming a plastic packaging material layer on a surface of the dielectric layer and a surface of the chip after the chip is flipped, where the plastic packaging material layer encloses the chip to form a packaging structure with the plastic packaging material layer; separating the carrier wafer and the peeling film from the packaging structure with the plastic packaging material layer, to form a plastic package wafer; soldering balls and reflowing to form solder ball bumps on a surface of the exposed metal electrode; and cutting in a monolithic manner to form a final fan out chip structure.
Practically, a package quality of the conventional fan out wafer level packaging method and an integration level of the formed packaging structure are to be improved.